Semiconductor device with metal gate

ABSTRACT

A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. patent application Ser. No.14/840,041, filed on Aug. 30, 2015, and all benefits of such earlierapplication are hereby claimed for this new continuation application.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The invention relates to a semiconductor device, and more particularlyto a semiconductor device with metal gate.

2. Description of the Prior Art

In current semiconductor industry, polysilicon has been widely used as agap-filling material for fabricating gate electrode ofmetal-oxide-semiconductor (MOS) transistors. However, the conventionalpolysilicon gate also faced problems such as inferior performance due toboron penetration and unavoidable depletion effect which increasesequivalent thickness of gate dielectric layer, reduces gate capacitance,and worsens driving force of the devices. In replacing polysilicongates, work function metals have been developed to serve as a controlelectrode working in conjunction with high-K gate dielectric layers.

Typically, threshold voltage in conventional planar metal gatetransistors is adjusted by the means of ion implantation. With the trendin the industry being towards scaling down the size of the metal oxidesemiconductor transistors (MOS), three-dimensional or non-planartransistor technology, such as fin field effect transistor technology(FinFET) has been developed to replace planar MOS transistors.Nevertheless, when electrical field applied onto a dielectric materialexceeds a threshold value, a sudden increase in the electrical currentpassing through the dielectric material would easily induce atime-dependent dielectric breakdown (TDDB) issue. Hence, how to resolvethis issue in today's FinFET architecture has become an important taskin this field.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a semiconductordevice includes a substrate and a gate structure on the substrate, inwhich the gate structure includes a high-k dielectric layer on thesubstrate and a bottom barrier metal (BBM) layer on the high-kdielectric layer. Preferably, the BBM layer includes a top portion, amiddle portion, and a bottom portion, the middle portion being anitrogen rich portion, the top portion and the bottom portion beingtitanium rich portions, and the top portion, the middle portion, and thebottom portion are of same material composition.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a method for fabricating semiconductor deviceaccording to a preferred embodiment of the present invention.

FIG. 2 illustrates an enlarged view of the BBM layer shown in FIG. 1.

FIG. 3 illustrates a structural view of a semiconductor device accordingto another embodiment of the present invention.

DETAILED DESCRIPTION

Referring to FIG. 1, FIG. 1 illustrates a method for fabricatingsemiconductor device according to a preferred embodiment of the presentinvention. As shown in FIG. 1, a substrate 12 is first provided, and agate structure 14 is formed on the substrate 12. The substrate 12 couldbe a silicon substrate, a silicon-containing substrate (such as SiCsubstrate), a GaN substrate, a GaN-on-silicon substrate, agraphene-on-silicon substrate, a SOI substrate or a substrate containingepitaxial layer (such as a p-type substrate containing p-type epitaxiallayer with 2.5 μm thickness).

The fabrication of the gate structure 14 could be accomplished by a gatefirst process, a high-k first approach from gate last process, or ahigh-k last approach from gate last process. Since this embodimentpertains to a high-k last approach, a dummy gate (not shown) composed ofinterfacial layer and polysilicon material could be first formed on thesubstrate 12, and a spacer 16 is formed on the sidewall of the dummygate. A source/drain region 18 and/or epitaxial layer (not shown) arethen formed in the substrate 12 adjacent to two sides of the spacer 16,a silicide layer (not shown) could be selectively formed on thesource/drain region 26 and/or epitaxial layer, a contact etch stop layer(CESL) 20 is formed on the dummy gate, and an interlayer dielectric(ILD) layer 22 composed of material such as tetraethyl orthosilicate(TEOS) is formed on the CESL 20.

Next, a replacement metal gate (RMG) process could be conducted to firstplanarize part of the ILD layer 22 and CESL 20 and then transform thedummy gate into the gate structure 14 composed of metal gate. The RMGprocess could be accomplished by first performing a selective dryetching or wet etching process, such as using etchants includingammonium hydroxide (NH₄OH) or tetramethylammonium hydroxide (TMAH) toremove the polysilicon material from dummy gate for forming a recess(not shown) in the ILD layer 22 and spacer 16.

Next, the interfacial layer in the dummy gate could be removed, andanother interfacial layer 24, a high-k dielectric layer 26, a bottombarrier metal (BBM) layer 28, a BBM layer 30, a work function metallayer 32, and a low resistance metal layer 34 are deposited into therecess. A planarizing process, such as CMP process is then conducted sothat the top surfaces of the high-k dielectric layer 26, BBM layer 28,BBM layer 30, work function metal layer 32, and low resistance metallayer 34 are coplanar. Since this embodiment pertains to a high-k lastprocess, the cross-sections of the high-k dielectric layer 26, BBM layer28, BBM layer 30, and work function layer 32 are U-shaped. If a high-kfirst approach were employed to transform the dummy gate into a metalgate, the cross-section of the high-k dielectric layer 26 is preferablyI-shaped while the cross-sections of the BBM layer 28, BBM layer 30, andwork function metal layer 32 are U-shaped, which is also within thescope of the present invention.

In this embodiment, the interfacial layer 24 is preferably composed ofoxides such as SiO₂, SiN, or SiON, but could also be composed of high-kdielectric material. The BBM layer 28 is preferably composed of TiN andthe BBM layer 30 is composed of TaN, but not limited thereto.

The high-k dielectric layer 26 is preferably selected from dielectricmaterials having dielectric constant (k value) larger than 4. Forinstance, the high-k dielectric layer 26 may be selected from hafniumoxide (HfO₂), hafnium silicon oxide (HfSiO₄), hafnium silicon oxynitride(HfSiON), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), tantalumoxide (Ta₂O₅), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), strontiumtitanate oxide (SrTiO₃), zirconium silicon oxide (ZrSiO₄), hafniumzirconium oxide (HfZrO₄), strontium bismuth tantalate (SrBi₂Ta₂O₉, SBT),lead zirconate titanate (PbZr_(x)Ti_(1-x)O₃, PZT), barium strontiumtitanate (Ba_(x)Sr_(1-x)TiO₃, BST) or a combination thereof.

In this embodiment, the work function metal layer 32 is formed fortuning the work function of the later formed metal gates to beappropriate in an NMOS or a PMOS. For an NMOS transistor, the workfunction metal layer 32 having a work function ranging between 3.9 eVand 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide(ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafniumaluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is notlimited thereto. For a PMOS transistor, the work function metal layer 32having a work function ranging between 4.8 eV and 5.2 eV may includetitanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC),but it is not limited thereto. An optional barrier layer (not shown)could be formed between the work function metal layer 32 and the lowresistance metal layer 34, in which the material of the barrier layermay include titanium (Ti), titanium nitride (TiN), tantalum (Ta) ortantalum nitride (TaN). Furthermore, the material of the low-resistancemetal layer 34 may include copper (Cu), aluminum (Al), titanium aluminum(TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.Since the process of using RMG process to transform dummy gate intometal gate is well known to those skilled in the art, the details ofwhich are not explained herein for the sake of brevity.

It should be noted that the nitrogen and titanium ratio of the BBM layer28 is adjusted during the deposition of the BBM layer 28 so thatdifferent parts of the BBM layer 28 could have different nitrogen totitanium ratio. Referring to FIG. 2, FIG. 2 illustrates an enlarged viewof the BBM layer 28 of FIG. 1. As shown in FIG. 2, the BBM layer 28could be composed of a top portion 36, a middle portion 38, and a bottomportion 40, in which the thickness of each of the top portion 36, middleportion 38, and bottom portion 40 is one third of the thickness of theentire BBM layer 38. In addition, the top portion 36 is a nitrogen richportion while each of the middle portion 38 and the bottom portion 40 isa titanium rich portion. If viewing from the nitrogen to titanium ratioperspective, the nitrogen-to-titanium ratio in the top portion 36 is1-1.2 to 1, the nitrogen-to-titanium ratio in the middle portion 38 is0.5-1 to 1, and the nitrogen-to-titanium ratio in the bottom portion 40is 0.5-1 to 1. In other words, the top portion 36 of BBM layer 28 inthis embodiment preferably includes higher nitrogen atom content whilethe middle portion 38 and bottom portion 40 include higher titanium atomcontent.

Referring to FIG. 3, FIG. 3 illustrates a structural view of the BBMlayer 28 of a semiconductor device according to another embodiment ofthe present invention. Similar to the aforementioned embodiment shown inFIG. 2, the BBM layer 28 is also divided into a top portion 36, a middleportion 38, and a bottom portion 40, in which the thickness of each ofthe top portion 36, middle portion 38, and bottom portion 40 is onethird of the total thickness of the BBM layer 28. In this embodiment,the middle portion 38 is a nitrogen rich portion while each of the topportion 36 and the bottom portion 40 is a titanium rich portion. Ifviewing from the nitrogen to titanium ratio perspective, thenitrogen-to-titanium ratio in the middle portion 38 is 1-1.2 to 1, thenitrogen-to-titanium ratio in the top portion 36 is 0.5-1 to 1, and thenitrogen-to-titanium ratio in the bottom portion 40 is 0.5-1 to 1. Inother words, the middle portion 38 of BBM layer 28 in this embodimentpreferably includes higher nitrogen atom content while the top portion36 and bottom portion 40 include higher titanium atom content.

Overall, the present invention provides two metal gate transistorstructures, in which the BBM layer composed of TiN in the metal gatepreferably includes a top portion, a middle portion, and a bottomportion. According to a first embodiment of the present invention, thetop portion of the BBM layer is a nitrogen rich portion while each ofthe middle portion and bottom portion is a titanium rich portion.According to a second embodiment of the present invention, the middleportion of the BBM layer is a nitrogen rich portion while each of thetop portion and bottom portion is a titanium rich portion. By employingthe aforementioned metal gate transistor structures, it would bedesirable to resolve the TDDB issue commonly found in current metal gatetransistors.

It should be noted that even though the aforementioned embodimentpertains to the BBM layer 28 consisting of TiN having multiple portionswhile BBM layer 30 consisting of TaN having only a single portion, itwould also be desirable to follow the aforementioned embodiment toadjust the nitrogen to tantalum ratio in the BBM layer 30 so that theBBM layer 30 could be divided into a top portion, a middle portion, anda bottom portion, in which each of the top portion, middle portion, andbottom portion could either be a nitrogen rich portion or a tantalumrich portion. For instance, it would be desirable to adjust the topportion of the BBM layer 30 to be a nitrogen rich portion while themiddle portion and bottom portion being tantalum rich portions, oradjust the middle portion of the BBM layer 30 to be a nitrogen richportion while the top portion and bottom portion being tantalum richportions, or adjust the bottom portion of the BBM layer 30 to be anitrogen rich portion while the top portion and middle portion beingtantalum rich portions, which are all within the scope of the presentinvention.

Moreover, despite the aforementioned embodiment pertains to a planartype transistor, it would also be desirable to employ the semiconductordevice of the present invention to non-planar transistors, such asFin-FET devices and in such instance, the substrate 12 shown in FIGS.1-3 would correspond to a fin-shaped structure atop a substrate, whichis also within the scope of the present invention.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A semiconductor device, comprising: a substrate;and a gate structure on the substrate, wherein the gate structurecomprises: a high-k dielectric layer on the substrate; and a bottombarrier metal (BBM) layer on the high-k dielectric layer, wherein theBBM layer comprises a top portion, a middle portion, and a bottomportion, the middle portion being a nitrogen rich portion, the topportion and the bottom portion being titanium rich portions, and the topportion, the middle portion, and the bottom portion are of same materialcomposition.
 2. The semiconductor device of claim 1, wherein thethickness of the top portion is one third of the thickness of the BBMlayer.
 3. The semiconductor device of claim 1, wherein the thickness ofthe middle portion is one third of the thickness of the BBM layer. 4.The semiconductor device of claim 1, wherein the thickness of the bottomportion is one third of the thickness of the BBM layer.
 5. Thesemiconductor device of claim 1, wherein the nitrogen-to-titanium ratioof the middle portion is 1:1.2 to 1:1.
 6. The semiconductor device ofclaim 1, wherein the nitrogen-to-titanium ratio in the top portion is0.5:1 to 1:1.
 7. The semiconductor device of claim 1, wherein thenitrogen-to-titanium ratio in the bottom portion is 0.5:1 to 1:1.